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Exploiting data encoding and reordering for low-power streaming in systolic arrays
(Elsevier, 2023-10-03)
Systolic Array (SA) architectures are well-suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data ...
Streaming Dilated Convolution Engine
(IEEE, 2023-01-09)
Convolution is one of the most critical operations in various application domains and its computation should combine high performance with energy efficiency. This requirement is critical both for standard convolution and ...
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
(IEEE, 2023-06-02)
Convolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performance and energy efficiency. In practice, the ...
Robustness of Artificial Neural Networks Based on Weight Alterations Used for Prediction Purposes
(MDPI, 2023-06-29)
Nowadays, due to their excellent prediction capabilities, the use of artificial neural networks (ANNs) in software has significantly increased. One of the most important aspects of ANNs
is robustness. Most existing studies ...
Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification
(IEEE, 2023-07-17)
Multi-armed bandit problems have recently received a great deal of attention, because they adequately formalize so called exploration-exploitation trade-offs arising in several relevant applications of recommendation ...
IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications
(IEEE, 2024-03)
Structured sparsity has been proposed as an efficient way to prune the complexity of modern Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. The acceleration of ML models - for ...
The Case for Asymmetric Systolic Array Floorplanning
(IEEE, 2023-09)
The widespread proliferation of deep learning applications has triggered the need to accelerate them directly in hardware. General Matrix Multiplication (GEMM) kernels are elemental deep-learning constructs and they ...
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines
(IEEE, 2023-07-07)
The acceleration of deep-learning kernels in hardware relies on matrix multiplications that are executed efficiently on Systolic Arrays (SA). To effectively trade off deep-learning training/inference quality with hardware ...
Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating
(IEEE, 2023-07-17)
Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data ...
Estimating the Performance Loss Rate of Photovoltaic Systems Using Time Series Change Point Analysis
(MDPI, 2023-04-26)
The accurate quantification of the performance loss rate of photovoltaic systems is critical
for project economics. Following the current research activities in the photovoltaic performance and
reliability field, this ...