DART: a data-driven processor architecture for real-time computing

Abstract

This paper presents the design of DART, a Data-driven processor Architecture for Real-Time computing. The DART processor is designed to be the key building block in real-time multiprocessor systems that can handle multiple 'hard' and 'soft' real-time processes concurrently. The DART processor is a data-flow/control-flow hybrid design that schedules instructions based not only on data availability but also on priority. The highest priority instruction having data available will be executed regardless of the thread in which it is contained. The DART processor retains fine grain actors but utilizes an operand forwarding scheme to reduce the latency between data dependent instructions in sequential threads. Data-driven context switch support is provided at the instruction level allowing for inordinately fast response and context switch time characteristics. These features provide the processor level support required to build a multiprocessor system, comprised of DART processing elements, specifically for real-time computing.