Browsing by Subject "Static random access storage"

Now showing items 1-3 of 3

    • Conference Object  

      An analytical model for the calculation of the Expected Miss Ratio in faulty caches 

      Sánchez, D.; Sazeides, Yiannakis; Aragón, J. L.; García, J. M. (2011)
      Technology scaling improvement is affecting the reliability of ICs due to increases in static and dynamic variations as well as wear-out failures. This is particularly true for caches that dominate the area of modern ...
    • Article  

      Modeling the impact of permanent faults in caches 

      Sánchez, D.; Sazeides, Yiannakis; Cebrián, J. M.; Garćia, J. M.; Aragón, J. L. (2013)
      The traditional performance cost benefits we have enjoyed for decades from technology scaling are challenged by several critical constraints including reliability. Increases in static and dynamic variations are leading to ...
    • Conference Object  

      RVC: A mechanism for time-analyzable real-time processors with faulty caches 

      Abella, J.; Quiñones, E.; Cazorla, F. J.; Sazeides, Yiannakis; Valero, M. (2011)
      Geometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ...