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Analysis of error recovery schemes for networks on chips

dc.contributor.authorMurali, S.en
dc.contributor.authorTheocharides, Theocharisen
dc.contributor.authorVijaykrishnan, N.en
dc.contributor.authorIrwin, M. J.en
dc.contributor.authorBenini, L.en
dc.contributor.authorDe Micheli, G.en
dc.creatorMurali, S.en
dc.creatorTheocharides, Theocharisen
dc.creatorVijaykrishnan, N.en
dc.creatorIrwin, M. J.en
dc.creatorBenini, L.en
dc.creatorDe Micheli, G.en
dc.date.accessioned2019-04-08T07:47:21Z
dc.date.available2019-04-08T07:47:21Z
dc.date.issued2005
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/44318
dc.sourceIEEE Design and Test of Computersen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-27344448860&doi=10.1109%2fMDT.2005.104&partnerID=40&md5=2bccd711312fe894bd55581bc58d25e4
dc.titleAnalysis of error recovery schemes for networks on chipsen
dc.typeinfo:eu-repo/semantics/article
dc.identifier.doi10.1109/MDT.2005.104
dc.description.volume22
dc.description.issue5
dc.description.startingpage434
dc.description.endingpage442
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeArticleen
dc.source.abbreviationIEEE Des.Test Comput.en
dc.contributor.orcidTheocharides, Theocharis [0000-0001-7222-9152]
dc.gnosis.orcid0000-0001-7222-9152


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