A Low-power network-on-chip architecture for tile-based chip multi-processors
Date
2016Author
Psarras, A.Lee, J.
Mattheakis, P.
Nicopoulos, Chrysostomos A.
Dimitrakopoulos, G.
Source
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSIProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume
18-20-May-2016Pages
335-340Google Scholar check