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The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices

dc.contributor.authorSolinas, M.en
dc.contributor.authorBadia, R. M.en
dc.contributor.authorBodin, F.en
dc.contributor.authorCohen, A.en
dc.contributor.authorEvripidou, Paraskevasen
dc.contributor.authorFaraboschi, P.en
dc.contributor.authorFechner, B.en
dc.contributor.authorGao, G. R.en
dc.contributor.authorGarbade, A.en
dc.contributor.authorGirbal, S.en
dc.contributor.authorGoodman, D.en
dc.contributor.authorKhan, B.en
dc.contributor.authorKoliai, S.en
dc.contributor.authorLi, F.en
dc.contributor.authorLuján, M.en
dc.contributor.authorMorin, L.en
dc.contributor.authorMendelson, A.en
dc.contributor.authorNavarro, N.en
dc.contributor.authorPop, A.en
dc.contributor.authorTrancoso, Pedroen
dc.contributor.authorUngerer, T.en
dc.contributor.authorValero, M.en
dc.contributor.authorWeis, S.en
dc.contributor.authorWatson, I.en
dc.contributor.authorZuckermann, S.en
dc.contributor.authorGiorgi, Robertoen
dc.creatorSolinas, M.en
dc.creatorBadia, R. M.en
dc.creatorBodin, F.en
dc.creatorCohen, A.en
dc.creatorEvripidou, Paraskevasen
dc.creatorFaraboschi, P.en
dc.creatorFechner, B.en
dc.creatorGao, G. R.en
dc.creatorGarbade, A.en
dc.creatorGirbal, S.en
dc.creatorGoodman, D.en
dc.creatorKhan, B.en
dc.creatorKoliai, S.en
dc.creatorLi, F.en
dc.creatorLuján, M.en
dc.creatorMorin, L.en
dc.creatorMendelson, A.en
dc.creatorNavarro, N.en
dc.creatorPop, A.en
dc.creatorTrancoso, Pedroen
dc.creatorUngerer, T.en
dc.creatorValero, M.en
dc.creatorWeis, S.en
dc.creatorWatson, I.en
dc.creatorZuckermann, S.en
dc.creatorGiorgi, Robertoen
dc.date.accessioned2019-11-13T10:42:19Z
dc.date.available2019-11-13T10:42:19Z
dc.date.issued2013
dc.identifier.isbn978-0-7695-5074-9
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/54994
dc.description.abstractThanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper describes the project and provides an overview of the research carried out by the TERAFLUX consortium. © 2013 IEEE.en
dc.sourceProceedings - 16th Euromicro Conference on Digital System Design, DSD 2013en
dc.source16th Euromicro Conference on Digital System Design, DSD 2013en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84890041280&doi=10.1109%2fDSD.2013.39&partnerID=40&md5=192f033c05d093c45bec6470eb5945c8
dc.subjectSimulationen
dc.subjectComputer simulationen
dc.subjectArchitectureen
dc.subjectSemiconductor device manufactureen
dc.subjectSystems analysisen
dc.subjectReliabilityen
dc.subjectMulticore programmingen
dc.subjectDataflowen
dc.subjectData flow analysisen
dc.subjectMany-coresen
dc.subjectProgramming modelen
dc.subjectProgramming modelsen
dc.subjectMulti-coresen
dc.subjectCompilationen
dc.subjectExascale computingen
dc.titleThe TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevicesen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1109/DSD.2013.39
dc.description.startingpage272
dc.description.endingpage279
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Conference code: 101116en
dc.description.notesCited By :15</p>en
dc.contributor.orcidTrancoso, Pedro [0000-0002-2776-9253]
dc.contributor.orcidEvripidou, Paraskevas [0000-0002-2335-9505]
dc.gnosis.orcid0000-0002-2776-9253
dc.gnosis.orcid0000-0002-2335-9505


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