Πλοήγηση Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering ανά Θέμα "Wafer sizes"
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Article
Information theoretic modeling and analysis for global interconnects with process variations
(2011)As the CMOS semiconductor technology enters nanometer regime, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. The resulting ubiquitous process ...