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dc.contributor.authorHadjicostis, Christoforos N.en
dc.creatorHadjicostis, Christoforos N.en
dc.date.accessioned2019-04-08T07:46:02Z
dc.date.available2019-04-08T07:46:02Z
dc.date.issued2005
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/43537
dc.description.abstractThis paper discusses a systematic methodology for calculating the exact aliasing probability associated with schemes that use an arbitrary finite-state machine to compact the response of a combinational circuit to a sequence of independently selected, random test input vectors. The proposed approach identifies the strong influence of fault activation probabilities on the probability of aliasing and uses an asymmetric error model to simultaneously track the states of two (fictitious) compactors, one driven by the response of the fault-free combinational circuit and one driven by the response of the faulty combinational circuit. By deriving the overall Markov chain that describes the combined behavior of these two compactors, we are able to calculate the exact aliasing probability for any test sequence length. In particular, for long enough sequences, the probability of aliasing is shown to only depend on the stationary distribution of the Markov chain. The insights provided by our analysis are used to evaluate the testing performance of simple examples of nonlinear compactors and to demonstrate regimes where they exhibit lower aliasing probability than linear compactors with the same number of states. Finally, by establishing connections with previous work that evaluated aliasing probability in linear compactors, our analysis clarifies the role played by the entropy of the stationary distribution of the compactor states. © 2005 IEEE.en
dc.sourceIEEE Transactions on Computersen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-30344473292&doi=10.1109%2fTC.2005.189&partnerID=40&md5=2ae1190e1419aa0a15478ca8f2985cce
dc.subjectMathematical modelsen
dc.subjectMarkov processesen
dc.subjectFinite automataen
dc.subjectProbability distributionsen
dc.subjectAliasing probabilityen
dc.subjectCombinatorial circuitsen
dc.subjectCompactionen
dc.subjectFault activation probabilitiesen
dc.subjectIntegrated circuit testingen
dc.subjectRandom testingen
dc.titleAliasing probability calculations for arbitrary compaction under independently selected random test vectorsen
dc.typeinfo:eu-repo/semantics/article
dc.identifier.doi10.1109/TC.2005.189
dc.description.volume54
dc.description.issue12
dc.description.startingpage1614
dc.description.endingpage1627
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeArticleen
dc.source.abbreviationIEEE Trans.Comput.en
dc.contributor.orcidHadjicostis, Christoforos N. [0000-0002-1706-708X]
dc.gnosis.orcid0000-0002-1706-708X


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