dc.contributor.author | Murali, S. | en |
dc.contributor.author | Theocharides, Theocharis | en |
dc.contributor.author | Vijaykrishnan, N. | en |
dc.contributor.author | Irwin, M. J. | en |
dc.contributor.author | Benini, L. | en |
dc.contributor.author | De Micheli, G. | en |
dc.creator | Murali, S. | en |
dc.creator | Theocharides, Theocharis | en |
dc.creator | Vijaykrishnan, N. | en |
dc.creator | Irwin, M. J. | en |
dc.creator | Benini, L. | en |
dc.creator | De Micheli, G. | en |
dc.date.accessioned | 2019-04-08T07:47:21Z | |
dc.date.available | 2019-04-08T07:47:21Z | |
dc.date.issued | 2005 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/44318 | |
dc.source | IEEE Design and Test of Computers | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-27344448860&doi=10.1109%2fMDT.2005.104&partnerID=40&md5=2bccd711312fe894bd55581bc58d25e4 | |
dc.title | Analysis of error recovery schemes for networks on chips | en |
dc.type | info:eu-repo/semantics/article | |
dc.identifier.doi | 10.1109/MDT.2005.104 | |
dc.description.volume | 22 | |
dc.description.issue | 5 | |
dc.description.startingpage | 434 | |
dc.description.endingpage | 442 | |
dc.author.faculty | Πολυτεχνική Σχολή / Faculty of Engineering | |
dc.author.department | Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering | |
dc.type.uhtype | Article | en |
dc.source.abbreviation | IEEE Des.Test Comput. | en |
dc.contributor.orcid | Theocharides, Theocharis [0000-0001-7222-9152] | |
dc.gnosis.orcid | 0000-0001-7222-9152 | |