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Design of a dynamic priority-based fast path architecture for on-chip interconnects

dc.contributor.authorPark, D.en
dc.contributor.authorDas, R.en
dc.contributor.authorNicopoulos, Chrysostomos A.en
dc.contributor.authorKim, J.en
dc.contributor.authorVijaykrishnan, N.en
dc.contributor.authorIyer, R.en
dc.contributor.authorDas, C. R.en
dc.creatorPark, D.en
dc.creatorDas, R.en
dc.creatorNicopoulos, Chrysostomos A.en
dc.creatorKim, J.en
dc.creatorVijaykrishnan, N.en
dc.creatorIyer, R.en
dc.creatorDas, C. R.en
dc.date.accessioned2019-04-08T07:47:42Z
dc.date.available2019-04-08T07:47:42Z
dc.date.issued2007
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/44535
dc.sourceProceedings - 15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnectsen
dc.sourceProceedings - 15th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnectsen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-46449125129&doi=10.1109%2fHOTI.2007.1&partnerID=40&md5=0e1234d9a09cec568fa18421aaf36279
dc.titleDesign of a dynamic priority-based fast path architecture for on-chip interconnectsen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1109/HOTI.2007.1
dc.description.startingpage15
dc.description.endingpage20
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeConference Objecten
dc.contributor.orcidNicopoulos, Chrysostomos [0000-0001-6389-6068]
dc.gnosis.orcid0000-0001-6389-6068


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