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A generic reconfigurable neural network architecture implemented as a network on chip

dc.contributor.authorTheocharides, Theocharisen
dc.contributor.authorLink, G.en
dc.contributor.authorVijaykrishnan, N.en
dc.contributor.authorIrwin, M. J.en
dc.contributor.authorSrikantam, V.en
dc.creatorTheocharides, Theocharisen
dc.creatorLink, G.en
dc.creatorVijaykrishnan, N.en
dc.creatorIrwin, M. J.en
dc.creatorSrikantam, V.en
dc.date.accessioned2019-04-08T07:48:26Z
dc.date.available2019-04-08T07:48:26Z
dc.date.issued2004
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/44944
dc.sourceProceedings - IEEE International SOC Conferenceen
dc.sourceProceedings - IEEE International SOC Conferenceen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-14844337467&partnerID=40&md5=679bfa961f5db05d026b0b4f89006c93
dc.titleA generic reconfigurable neural network architecture implemented as a network on chipen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.description.startingpage191
dc.description.endingpage194
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeConference Objecten
dc.contributor.orcidTheocharides, Theocharis [0000-0001-7222-9152]
dc.gnosis.orcid0000-0001-7222-9152


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