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Hardware design considerations for edge-accelerated stereo correspondence algorithms

dc.contributor.authorTtofis, C.en
dc.contributor.authorTheocharides, Theocharisen
dc.creatorTtofis, C.en
dc.creatorTheocharides, Theocharisen
dc.date.accessioned2019-04-08T07:48:34Z
dc.date.available2019-04-08T07:48:34Z
dc.date.issued2012
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/45009
dc.sourceVLSI Designen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84862286549&doi=10.1155%2f2012%2f602737&partnerID=40&md5=e0b9b523c400f0c96b1e80b94df17da5
dc.titleHardware design considerations for edge-accelerated stereo correspondence algorithmsen
dc.typeinfo:eu-repo/semantics/article
dc.identifier.doi10.1155/2012/602737
dc.description.volume2012
dc.description.issueJournal Articleen
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeArticleen
dc.source.abbreviationVLSI Desen
dc.contributor.orcidTheocharides, Theocharis [0000-0001-7222-9152]
dc.gnosis.orcid0000-0001-7222-9152


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