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Variation-aware task and communication mapping for MPSoC architecture

dc.contributor.authorWang, F.en
dc.contributor.authorChen, Y.en
dc.contributor.authorNicopoulos, Chrysostomos A.en
dc.contributor.authorWu, X.en
dc.contributor.authorXie, Y.en
dc.contributor.authorVijaykrishnan, N.en
dc.creatorWang, F.en
dc.creatorChen, Y.en
dc.creatorNicopoulos, Chrysostomos A.en
dc.creatorWu, X.en
dc.creatorXie, Y.en
dc.creatorVijaykrishnan, N.en
dc.date.accessioned2019-04-08T07:48:41Z
dc.date.available2019-04-08T07:48:41Z
dc.date.issued2011
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/45075
dc.sourceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-78951489090&doi=10.1109%2fTCAD.2010.2077830&partnerID=40&md5=b640e7abed651f074a059cd95b724ac1
dc.titleVariation-aware task and communication mapping for MPSoC architectureen
dc.typeinfo:eu-repo/semantics/article
dc.identifier.doi10.1109/TCAD.2010.2077830
dc.description.volume30
dc.description.issue2
dc.description.startingpage295
dc.description.endingpage307
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeArticleen
dc.source.abbreviationIEEE Trans Comput Aided Des Integr Circuits Systen
dc.contributor.orcidNicopoulos, Chrysostomos [0000-0001-6389-6068]
dc.gnosis.orcid0000-0001-6389-6068


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