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dc.contributor.authorHardy, D.en
dc.contributor.authorPuaut, I.en
dc.contributor.authorSazeides, Yiannakisen
dc.creatorHardy, D.en
dc.creatorPuaut, I.en
dc.creatorSazeides, Yiannakisen
dc.description.abstractFine-grained disabling and reconfiguration of hardware elements (functional units, cache blocks) will become economically necessary to recover from permanent failures, whose rate is expected to increase dramatically in the near future. This fine-grained disabling will lead to degraded performance as compared to a fault-free execution. Until recently, all static worst-case execution time (WCET) estimations methods were assuming fault-free processors, resulting in unsafe estimates in the presence of faults. The first static WCET estimation technique dealing with the presence of permanent faults in instruction caches was proposed in [1]. This study probabilistically quantified the impact of permanent faults on WCET estimates. It demonstrated that the probabilistic WCET (pWCET) estimates of tasks increase rapidly with the probability of faults as compared to fault-free WCET estimates. In this paper, we show that very simple reliability mechanisms allow mitigating the impact of faulty cache blocks on pWCETs. Two mechanisms, that make part of the cache resilient to faults are analyzed. Experiments show that the gain in pWCET for these two mechanisms are on average 48% and 40% as compared to an architecture with no reliability mechanism. © 2016 EDAA.en
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en
dc.sourceProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016en
dc.source19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016en
dc.subjectReconfigurable hardwareen
dc.subjectWorst-case execution timeen
dc.subjectCache blocksen
dc.subjectDegraded performanceen
dc.subjectEstimation techniquesen
dc.subjectFunctional unitsen
dc.subjectHardware elementsen
dc.subjectInstruction cachesen
dc.subjectPermanent faultsen
dc.titleProbabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faultsen
dc.description.endingpage96 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: Ciscoen
dc.description.noteset al.en
dc.description.notesGoethe Universitat Frankfurten
dc.description.notesTechnische Universitat Dresdenen
dc.description.notesConference code: 121520en
dc.description.notesCited By :5</p>en

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