dc.contributor.author | Kleanthous, Marios M. | en |
dc.contributor.author | Sazeides, Yiannakis | en |
dc.creator | Kleanthous, Marios | en |
dc.creator | Sazeides, Yiannakis | en |
dc.date.accessioned | 2019-11-13T10:40:43Z | |
dc.date.available | 2019-11-13T10:40:43Z | |
dc.date.issued | 2011 | |
dc.identifier.issn | 1544-3566 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/54263 | |
dc.description.abstract | Cache-content-duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different tag. Caches aware of content-duplication can have lower miss penalty by fetching, on a miss to a duplicate block, directly from the cache instead of accessing lower in the memory hierarchy, and can have lower miss rates by allowing only blocks with unique content to enter a cache. This work examines the potential of CCD for instruction caches. We show that CCD is a frequent phenomenon and that an idealized duplication-detection mechanism for instruction caches has the potential to increase performance of an out-of-order processor, with a 16KB, 8-way, 8 instructions per block instruction cache, often by more than 10% and up to 36%. This work also proposes CATCH, a hardware mechanism for dynamically detecting CCD for instruction caches. Experimental results for an out-of-order processor show that a duplication-detection mechanism with a 1.38KB cost captureson average 58% of the CCD's idealized potential. © 2011 ACM. | en |
dc.source | Transactions on Architecture and Code Optimization | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-80455127311&doi=10.1145%2f2019608.2019610&partnerID=40&md5=924dcb95008acccded4da3e6a8eea738 | |
dc.subject | Cache memory | en |
dc.subject | Microprocessor chips | en |
dc.subject | Hardware mechanism | en |
dc.subject | Instruction caches | en |
dc.subject | Cache compression | en |
dc.subject | Cache content duplication. | en |
dc.subject | Cache optimizations | en |
dc.subject | Memory hierarchy | en |
dc.subject | Miss-rate | en |
dc.subject | Out-of-order processors | en |
dc.title | CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches | en |
dc.type | info:eu-repo/semantics/article | |
dc.identifier.doi | 10.1145/2019608.2019610 | |
dc.description.volume | 8 | |
dc.description.issue | 3 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Article | en |
dc.description.notes | <p>Cited By :1</p> | en |
dc.source.abbreviation | Trans.Archit.Code Optim. | en |