Show simple item record

dc.contributor.authorMatheou, Georgeen
dc.contributor.authorEvripidou, Paraskevasen
dc.creatorMatheou, Georgeen
dc.creatorEvripidou, Paraskevasen
dc.date.accessioned2019-11-13T10:41:10Z
dc.date.available2019-11-13T10:41:10Z
dc.date.issued2013
dc.identifier.isbn978-1-4799-0103-6
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/54481
dc.description.abstractData-Driven Multithreading (DDM) is a threaded data-flow model that schedules threads for execution based on data availability. DDM is utilizing a Thread Scheduling Unit (TSU) for the management of the threads on sequential processors. In this work we present the hardware implementation of the TSU with synthesizable code using the Verilog HDL and its evaluation using the ISim simulator. The evaluation results show that the TSU is able to run at a maximum frequency of 180 MHz and consumes only 5% of the Xilinx Virtex-6 FPGA resources. The initial results obtained in this work will enable us to design an FPGA based DDM multicore chip consisting of several Microblaze cores driven by the TSU. Thus, we will be able to evaluate the performance of the novel threaded data-flow model and have direct comparison with the sequential model on the same hardware. © 2013 IEEE.en
dc.publisherIEEE Computer Societyen
dc.sourceProceedings - 2013 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2013en
dc.source2013 13th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2013en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84888873771&doi=10.1109%2fSAMOS.2013.6621136&partnerID=40&md5=e40fa9598fdb68cc3f2a228aca92d9b2
dc.subjectComputer simulationen
dc.subjectHardwareen
dc.subjectHardware implementationsen
dc.subjectSchedulingen
dc.subjectField programmable gate arrays (FPGA)en
dc.subjectEvaluation resultsen
dc.subjectData-driven multithreadingen
dc.subjectMulti-core systemsen
dc.subjectThread schedulingen
dc.subjectComputer hardware description languagesen
dc.subjectHardware supportsen
dc.subjectSequential processorsen
dc.subjectMaximum frequencyen
dc.titleVerilog-based simulation of hardware support for Data-flow concurrency on Multicore systemsen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1109/SAMOS.2013.6621136
dc.description.startingpage280
dc.description.endingpage287
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors:en
dc.description.notesConference code: 101022en
dc.description.notesCited By :1</p>en
dc.contributor.orcidEvripidou, Paraskevas [0000-0002-2335-9505]
dc.contributor.orcidMatheou, George [0000-0002-3019-7102]
dc.gnosis.orcid0000-0002-2335-9505
dc.gnosis.orcid0000-0002-3019-7102


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record