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dc.contributor.authorSazeides, Yiannakisen
dc.creatorSazeides, Yiannakisen
dc.date.accessioned2019-11-13T10:42:10Z
dc.date.available2019-11-13T10:42:10Z
dc.date.issued2002
dc.identifier.isbn0-7695-1525-8
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/54930
dc.description.abstractSeveral studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described in an ambiguous manner, mainly due to the lack of formalization that defines the effects of value-speculation on a microarchitecture. In particular, the manifestations of value-speculation on the latency of microarchitectural operations, such as releasing resources and reissuing, was at best partially addressed. This may be problematic since results obtained in these studies can be difficult to reproduce and/or appreciate their contribution. This paper introduces a model for a methodical description of dynamically-scheduled microarchitectures that use value-speculation. The model isolates the parts of a microarchitecture that may be influenced by value-speculation in terms of various variables and latency events. This provides systematic means for describing, evaluating and comparing the,performance of value-speculative microarchitectures. The model parameters are integrated in a simulator to investigate the performance of several value-speculation related events. Among other, the results show value-speculation performance to have non-uniform sensitivity to changes in the latency of these events. For example, fast verification latency is found to be essential, but when mis-speculation is infrequent slow invalidation may be acceptable. © 2002 IEEE.en
dc.publisherIEEE Computer Societyen
dc.sourceProceedings - International Symposium on High-Performance Computer Architectureen
dc.source8th International Symposium on High-Performance Computer Architecture, HPCA 2002en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-33644599693&doi=10.1109%2fHPCA.2002.995711&partnerID=40&md5=49af13bad79cf366251d27f7ba3eb2ff
dc.subjectComputer softwareen
dc.subjectComputer architectureen
dc.subjectDiscrete event simulationen
dc.subjectHardwareen
dc.subjectDelayen
dc.subjectMicroarchitectureen
dc.subjectParallel processingen
dc.subjectComputer hardwareen
dc.subjectComputer scienceen
dc.subjectSupercomputersen
dc.subjectApplication programsen
dc.subjectProgram processorsen
dc.subjectCounting circuitsen
dc.subjectDelay circuitsen
dc.subjectApplication softwareen
dc.subjectMicro architecturesen
dc.subjectRegistersen
dc.subjectSoftware performanceen
dc.titleModeling value speculationen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1109/HPCA.2002.995711
dc.description.volume2002-Januaryen
dc.description.startingpage211
dc.description.endingpage222
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: Compaqen
dc.description.notesIEEE Computer Society Technical Committee on Computer Architectureen
dc.description.notesIntelen
dc.description.notesVirtutechen
dc.description.notesConference code: 115794en
dc.description.notesCited By :5</p>en


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