dc.contributor.author | Trancoso, Pedro | en |
dc.contributor.author | Evripidou, Paraskevas | en |
dc.contributor.author | Stavrou, Kyriakos | en |
dc.contributor.author | Kyriacou, Costas | en |
dc.creator | Trancoso, Pedro | en |
dc.creator | Evripidou, Paraskevas | en |
dc.creator | Stavrou, Kyriakos | en |
dc.creator | Kyriacou, Costas | en |
dc.date.accessioned | 2019-11-13T10:42:30Z | |
dc.date.available | 2019-11-13T10:42:30Z | |
dc.date.issued | 2006 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/55078 | |
dc.description.abstract | Current high-end microprocessors achieve high performance as a result of adding more features and therefore increasing complexity. This paper makes the case for a Chip-Multiprocessor based on the Data-Driven Multithreading (DDM-CMP) execution model in order to overcome the limitations of current design trends. Data-Driven Multithreading (DDM) is a multithreading model that effectively hides the communication delay and synchronization overheads. DDM-CMP avoids the complexity of other designs by combining simple commodity microprocessors with a small hardware overhead for thread scheduling and an interconnection network. Preliminary experimental results show that a DDM-CMP chip of the same hardware budget as a high-end commercial microprocessor, clocked at the same frequency, achieves a speedup of up to 18.5 with a 78-81% power consumption of the commercial chip. Overall, the estimated results for the proposed DDM-CMP architecture show a significant benefit in terms of both speedup and power consumption making it an attractive architecture for future processors. © 2006 Springer Science+Business Media, Inc. | en |
dc.source | International Journal of Parallel Programming | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33746597859&doi=10.1007%2fs10766-006-0016-z&partnerID=40&md5=bdaa7d0a27ccf8d06962c2303239e6bf | |
dc.subject | Mathematical models | en |
dc.subject | Synchronization | en |
dc.subject | Interconnection networks | en |
dc.subject | Parallel processing systems | en |
dc.subject | Parallel processing | en |
dc.subject | Data acquisition | en |
dc.subject | Microprocessor chips | en |
dc.subject | Multithreading | en |
dc.subject | Delay circuits | en |
dc.subject | Chip multiprocessor | en |
dc.subject | Data-driven execution | en |
dc.title | A case for chip multiprocessors based on the data-driven multithreading model | en |
dc.type | info:eu-repo/semantics/article | |
dc.identifier.doi | 10.1007/s10766-006-0016-z | |
dc.description.volume | 34 | |
dc.description.issue | 3 | |
dc.description.startingpage | 213 | |
dc.description.endingpage | 235 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Article | en |
dc.description.notes | <p>Cited By :5</p> | en |
dc.source.abbreviation | Int J Parallel Program | en |
dc.contributor.orcid | Evripidou, Paraskevas [0000-0002-2335-9505] | |
dc.contributor.orcid | Trancoso, Pedro [0000-0002-2776-9253] | |
dc.gnosis.orcid | 0000-0002-2335-9505 | |
dc.gnosis.orcid | 0000-0002-2776-9253 | |