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Monitor and Knob Techniques in Network-on-Chip Architectures

dc.contributor.authorZoni, Davideen
dc.contributor.authorEnglezakis, Panayiotisen
dc.contributor.authorChrysanthou, Kyprosen
dc.contributor.authorCanidio, Andreaen
dc.contributor.authorProdromou, Andreasen
dc.contributor.authorPanteli, Andreasen
dc.contributor.authorNicopoulos, Chrysostomosen
dc.contributor.authorDimitrakopoulos, Giorgosen
dc.contributor.authorSazeides, Yiannakisen
dc.contributor.authorFornaciari, Williamen
dc.contributor.editorFornaciari, Williamen
dc.contributor.editorSoudris, Dimitriosen
dc.coverage.spatialChamen
dc.creatorZoni, Davideen
dc.creatorEnglezakis, Panayiotisen
dc.creatorChrysanthou, Kyprosen
dc.creatorCanidio, Andreaen
dc.creatorProdromou, Andreasen
dc.creatorPanteli, Andreasen
dc.creatorNicopoulos, Chrysostomosen
dc.creatorDimitrakopoulos, Giorgosen
dc.creatorSazeides, Yiannakisen
dc.creatorFornaciari, Williamen
dc.date.accessioned2021-01-26T09:45:14Z
dc.date.available2021-01-26T09:45:14Z
dc.date.issued2019
dc.identifier.isbn978-3-319-91962-1
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/63149
dc.description.abstractThis chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the BlackOut architecture is a fine-grained power-gating methodology targeting individual router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the system performanceen
dc.description.abstract(b) the NoCAlert framework is a comprehensive on-line and real-time fault-detection and localization mechanism. Based on the concept of invariance checking, NoCAlert employs a group of lightweight micro-checker modules that collectively implement real-tim5e hardware assertions. Overall, the two solutions demonstrate the potential for ultrafast and low-cost monitor-and-knob mechanisms that can be applied to the NoC of multi-/many-core chips.en
dc.language.isoenen
dc.publisherSpringer International Publishingen
dc.sourceHarnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms: A Cross-layer Approachen
dc.source.urihttps://doi.org/10.1007/978-3-319-91962-1_9
dc.titleMonitor and Knob Techniques in Network-on-Chip Architecturesen
dc.typeinfo:eu-repo/semantics/bookChapter
dc.description.startingpage187
dc.description.endingpage213
dc.author.facultyΠολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeBook Chapteren
dc.contributor.orcidSoudris, Dimitrios [0000-0002-6930-6847]
dc.contributor.orcidNicopoulos, Chrysostomos [0000-0001-6389-6068]
dc.contributor.orcidProdromou, Andreas [0000-0002-2150-4799]
dc.contributor.orcidDimitrakopoulos, Giorgos [0000-0003-3688-7865]
dc.gnosis.orcid0000-0002-6930-6847
dc.gnosis.orcid0000-0001-6389-6068
dc.gnosis.orcid0000-0002-2150-4799
dc.gnosis.orcid0000-0003-3688-7865


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