dc.contributor.author | Konstantinou, Dimitris | en |
dc.contributor.author | Psarras, Anastasios | en |
dc.contributor.author | Dimitrakopoulos, Giorgos | en |
dc.contributor.author | Nicopoulos, Chrysostomos | en |
dc.creator | Konstantinou, Dimitris | en |
dc.creator | Psarras, Anastasios | en |
dc.creator | Dimitrakopoulos, Giorgos | en |
dc.creator | Nicopoulos, Chrysostomos | en |
dc.date.accessioned | 2021-01-26T09:45:50Z | |
dc.date.available | 2021-01-26T09:45:50Z | |
dc.date.issued | 2018 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/63419 | |
dc.description.abstract | Latency-insensitive data flow is a design paradigm that tolerates the latency variability of computations and communications and allows for correct-by-construction module integration. In this paper, we aim to reduce the dynamic power consumption of synchronous latency-insensitive systems by reducing the power of their clock network. In order to save on clocking power, we employ a Dual-Edge-Triggered (DET) clocking strategy and flow-control rules, whereby the clock operates at half the clock frequency, and data flow occurs on both rising and falling clock transitions. To support this operation, new low-cost DET elastic buffers are proposed that allow for full-throughput operation using only two latches per buffer, and without incurring any additional overhead relative to their baseline single-edge-triggered counterparts. Hence, the two design elements (flow control and elastic buffers) work synergistically to yield a highly efficient fundamental primitive building block that can seamlessly facilitate DET clocking in latency-insensitive systems. | en |
dc.source | 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST) | en |
dc.title | Low-power dual-edge-triggered synchronous latency-insensitive systems | en |
dc.type | info:eu-repo/semantics/conferenceObject | |
dc.identifier.doi | 10.1109/MOCAST.2018.8376625 | |
dc.description.startingpage | 1 | |
dc.description.endingpage | 4 | |
dc.author.faculty | Πολυτεχνική Σχολή / Faculty of Engineering | |
dc.author.department | Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering | |
dc.type.uhtype | Conference Object | en |
dc.contributor.orcid | Nicopoulos, Chrysostomos [0000-0001-6389-6068] | |
dc.contributor.orcid | Dimitrakopoulos, Giorgos [0000-0003-3688-7865] | |
dc.contributor.orcid | Psarras, Anastasios [0000-0001-6151-9242] | |
dc.gnosis.orcid | 0000-0001-6389-6068 | |
dc.gnosis.orcid | 0000-0003-3688-7865 | |
dc.gnosis.orcid | 0000-0001-6151-9242 | |