Low-power dual-edge-triggered synchronous latency-insensitive systems

Abstract

Latency-insensitive data flow is a design paradigm that tolerates the latency variability of computations and communications and allows for correct-by-construction module integration. In this paper, we aim to reduce the dynamic power consumption of synchronous latency-insensitive systems by reducing the power of their clock network. In order to save on clocking power, we employ a Dual-Edge-Triggered (DET) clocking strategy and flow-control rules, whereby the clock operates at half the clock frequency, and data flow occurs on both rising and falling clock transitions. To support this operation, new low-cost DET elastic buffers are proposed that allow for full-throughput operation using only two latches per buffer, and without incurring any additional overhead relative to their baseline single-edge-triggered counterparts. Hence, the two design elements (flow control and elastic buffers) work synergistically to yield a highly efficient fundamental primitive building block that can seamlessly facilitate DET clocking in latency-insensitive systems.