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dc.contributor.authorPeltekis, Christodoulosen
dc.contributor.authorFilippas, Dionysiosen
dc.contributor.authorDimitrakopoulos, Giorgosen
dc.contributor.authorNicopoulos, Chrysostomosen
dc.contributor.authorPnevmatikatos, Dionisiosen
dc.creatorPeltekis, Christodoulosen
dc.creatorFilippas, Dionysiosen
dc.creatorDimitrakopoulos, Giorgosen
dc.creatorNicopoulos, Chrysostomosen
dc.creatorPnevmatikatos, Dionisiosen
dc.date.accessioned2023-12-19T16:51:14Z
dc.date.available2023-12-19T16:51:14Z
dc.date.issued2023-06-02
dc.identifier.issn1558-1101
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/65826en
dc.description.abstractConvolutional Neural Networks (CNNs) are the state-of-the-art solution for many deep learning applications. For maximum scalability, their computation should combine high performance and energy efficiency. In practice, the convolutions of each CNN layer are mapped to a matrix multiplication that includes all input features and kernels of each layer and is computed using a systolic array. In this work, we focus on the design of a systolic array with configurable pipeline with the goal to select an optimal pipeline configuration for each CNN layer. The proposed systolic array, called ArrayFlex, can operate in normal, or in shallow pipeline mode, thus balancing the execution time in cycles and the operating clock frequency. By selecting the appropriate pipeline configuration per CNN layer, ArrayFlex reduces the inference latency of state-of-the-art CNNs by 11 %, on average, as compared to a traditional fixed-pipeline systolic array. Most importantly, this result is achieved while using 13 %-23 % less power, for the same applications, thus offering a combined energy-delay-product efficiency between 1.4× and 1.8× .en
dc.language.isoengen
dc.publisherIEEEen
dc.sourceDesign, Automation & Test in Europe Conference & Exhibition (DATE) 2023en
dc.source.urihttps://doi.org/10.23919/DATE56975.2023.10136913en
dc.source.urihttps://ieeexplore.ieee.org/abstract/document/10136913en
dc.titleArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipeliningen
dc.typeinfo:eu-repo/semantics/articleen
dc.identifier.doi10.23919/DATE56975.2023.10136913
dc.author.faculty007 Πολυτεχνική Σχολή / Faculty of Engineering
dc.author.departmentΤμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering
dc.type.uhtypeArticleen
dc.contributor.orcidNicopoulos, Chrysostomos [0000-0001-6389-6068]
dc.contributor.orcidFilippas, Dionysios [0000-0002-4729-3336]
dc.contributor.orcidDimitrakopoulos, Giorgos [0000-0003-3688-7865]
dc.contributor.orcidPnevmatikatos, Dionisios [0000-0003-3533-2761]
dc.type.subtypeCONFERENCE_PROCEEDINGSen
dc.gnosis.orcid0000-0001-6389-6068
dc.gnosis.orcid0000-0002-4729-3336
dc.gnosis.orcid0000-0003-3688-7865
dc.gnosis.orcid0000-0003-3533-2761


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