Browsing by Subject "Multi-cores"

Now showing items 1-6 of 6

    • Article  

      BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 

      Zoni, D.; Canidio, A.; Fornaciari, W.; Englezakis, Panayiotis; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis (2017)
      The Network-on-Chip (NoC) router buffers play an instrumental role in the performance of both the interconnection fabric and the entire multi-/many-core system. Nevertheless, the buffers also constitute the major leakage ...
    • Conference Object  

      Integrating transactions into the data-driven multi-threading model using the tflux platform 

      Diavastos, Andreas; Trancoso, Pedro; Luján, M.; Watson, I. (2012)
      Multi-core processors have renewed interest in programming models which can efficiently exploit general purpose parallelism. Data-Flow is one such model which has demonstrated significant potential in the past. However, ...
    • Conference Object  

      Scalable and dynamic global power management for multicore chips 

      Otoom, M.; Trancoso, Pedro; Almasaeid, H.; Alzubaidi, M. (Association for Computing Machinery, 2015)
      The design for continuous computer performance is increasingly becoming limited by the exponential increase in the power consumption. In order to improve the energy efficiency of multicore chips, we propose a novel global ...
    • Conference Object  

      The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices 

      Solinas, M.; Badia, R. M.; Bodin, F.; Cohen, A.; Evripidou, Paraskevas; Faraboschi, P.; Fechner, B.; Gao, G. R.; Garbade, A.; Girbal, S.; Goodman, D.; Khan, B.; Koliai, S.; Li, F.; Luján, M.; Morin, L.; Mendelson, A.; Navarro, N.; Pop, A.; Trancoso, Pedro; Ungerer, T.; Valero, M.; Weis, S.; Watson, I.; Zuckermann, S.; Giorgi, Roberto (2013)
      Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably ...
    • Article  

      TERAFLUX: Harnessing dataflow in next generation teradevices 

      Giorgi, Roberto; Badia, R. M.; Bodin, F.; Cohen, A.; Evripidou, Paraskevas; Faraboschi, P.; Fechner, B.; Gao, G. R.; Garbade, A.; Gayatri, R.; Girbal, S.; Goodman, D.; Khan, B.; Koliaï, S.; Landwehr, J.; Lê, N. M.; Li, F.; Lujàn, M.; Mendelson, A.; Morin, L.; Navarro, N.; Patejko, T.; Pop, A.; Trancoso, Pedro; Ungerer, T.; Watson, I.; Weis, S.; Zuckerman, S.; Valero, M. (2014)
      The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been ...
    • Conference Object  

      Using personality metrics to improve cache interference management in multicore processors 

      Otoom, M.; Jaleel, A.; Trancoso, Pedro (Association for Computing Machinery, Inc, 2017)
      The trend of increasing the number of cores in a processor will lead to certain challenges, among which the fact that more cores issue more memory requests and this in turn will increase the competition, or interference, ...