Power-aware Error Detection Schemes for Memory Arrays

Abstract

Achieving fault tolerance is an inevitable problem in architectural arrays such as caches, which it becoming more challenging with the power constrains. This work propose to reduce energy by avoiding access to columns of on-chip SRAM arrays whose cell contents used to store the bits for error protection. We refer to this approach as Error Detection Code Sharing that relies on a lazy-based method for fault detection. We explain how the EDCS approach can be leveraged to reduce the energy needed for Error Detection Codes. Experimental analysis reveal that the proposed scheme can leverage to reduce the energy. The potential energy savings of the propose approach at 32nm often exceeds 7% for several processor arrays. The energy savings however may come at the expense of lower fault–detection coverage. This work also proposes, EDCS-LC, an approach in lie with the EDCS that uses one vector to keep track of the codes that appear in the cache to further increase the fault detection coverage with no impact on the energy savings that EDCS technique provides.