Performance and power optimization through data compression in Network-on-Chip architectures

Conference Object

Date

2008

Author

Das, R.
Mishra, A. K.

Nicopoulos, Chrysostomos A.
Park, D.
Narayanan, V.
Iyer, R.
Yousif, M. S.
Das, C. R.

Source

2008 IEEE 14th International Symposium on High Performance Computer Architecture

Pages

215-225

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Keyword(s):

Cache compression

Communication compression

Data compression

Energy behavior

Energy consumption

Microarchitecture

Multicore processing

Network routing

Network-on-a-chip

Network-on-chip

Network-on-chip architecture

Noc communication latency

Noc performance

Nonuniform cache-based multicore architectures

Packet-based network-on-chip

Power consumption

Power optimization

Router architecture

Storage compression

Metadata

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DOI

10.1109/HPCA.2008.4658641

URI

http://gnosis.library.ucy.ac.cy/handle/7/43253

Collections

Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών / Department of Electrical and Computer Engineering [2853]

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