Implementation of IEEE single precision floating point addition and multiplication on FPGAs
AuthorLouca, Loucas S.
Cook, Todd A.
Johnson, William H.
PublisherAffiliation: Rutgers Univ, Piscataway, United States
Correspondence Address: Louca, Loucas
Rutgers Univ, Piscataway, United States
SourceIEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
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Floating point operations are hard to implement on FPGAs because of the complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, we have explored FPGA implementations of addition and multiplication for IEEE single precision floating-point numbers. Customizations were performed where this was possible in order to save chip area, or get the most out of our prototype board. The implementations tradeoff area and speed for accuracy. The adder is a bit-parallel adder, and the multiplier is a digit-serial multiplier. Prototypes have been implemented on Altera FLEX8000s, and peak rates of 7MFlops for 32-bit addition and 2.3MFlops for 32-bit multiplication have been obtained.