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dc.contributor.authorAhsan, B.en
dc.contributor.authorNdreu, L.en
dc.contributor.authorSideris, I.en
dc.contributor.authorSazeides, Yiannakisen
dc.contributor.authorIdgunji, S.en
dc.contributor.authorÖzer, E.en
dc.creatorAhsan, B.en
dc.creatorNdreu, L.en
dc.creatorSideris, I.en
dc.creatorSazeides, Yiannakisen
dc.creatorIdgunji, S.en
dc.creatorÖzer, E.en
dc.description.abstractThis work proposes to reduce energy by avoiding access to columns of on-chip SRAM arrays whose cell contents are all 1s or all 0s. We refer to this dynamic phenomenon as the Same-Cell-Content-Column (SCC-column). Analysis reveals that SCC-columns occur frequently in several processor arrays, such as tag arrays of L1 caches, TLBs and predictors. An interval based scheme that employs one bit per column is proposed to track whether we have a SCC-column. We explain how a SCC-column can be leveraged to reduce the energy needed for SRAM read and write accesses. Experimental analysis for a specific processor configuration reveals that the proposed scheme detects SCC-columns effectively. The potential energy savings of the proposed approach at 32nm often exceeds 40% for several processor arrays. © 2011 IEEE.en
dc.sourceProceedings of the International Symposium on Low Power Electronics and Designen
dc.source17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011en
dc.subjectPower electronicsen
dc.subjectDynamic phenomenaen
dc.subjectExperimental analysisen
dc.subjectLow power electronicsen
dc.subjectOn chipsen
dc.subjectProcessor arrayen
dc.subjectSpecific processoren
dc.subjectTag arraysen
dc.titleEliminating energy of same-content-cell-columns of on-chip SRAM arraysen
dc.description.endingpage186 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Conference code: 86471en
dc.description.notesCited By :3</p>en

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