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dc.contributor.authorDikaiakos, Marios D.en
dc.contributor.authorSteiglitz, K.en
dc.creatorDikaiakos, Marios D.en
dc.creatorSteiglitz, K.en
dc.date.accessioned2019-11-13T10:39:52Z
dc.date.available2019-11-13T10:39:52Z
dc.date.issued1991
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/53846
dc.description.abstractA critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. © 1991 Kluwer Academic Publishers.en
dc.sourceJournal of VLSI Signal Processingen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-0026154429&doi=10.1007%2fBF00925471&partnerID=40&md5=39e34433699df346eeb18b96d54bf7af
dc.subjectPipelinesen
dc.subjectFailure Analysisen
dc.subjectElectronic Circuits, Timingen
dc.subjectSignal Processingen
dc.subjectStraight Line Clockingen
dc.subjectSystolic Arraysen
dc.subjectTiming Buffersen
dc.subjectTree Clockingen
dc.titleComparison of tree and straight-line clocking for long systolic arraysen
dc.typeinfo:eu-repo/semantics/article
dc.identifier.doi10.1007/BF00925471
dc.description.volume2
dc.description.issue4
dc.description.startingpage287
dc.description.endingpage299
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeArticleen
dc.source.abbreviationJ VLSI Sign Process Syst Sign Image Video Technolen
dc.contributor.orcidDikaiakos, Marios D. [0000-0002-4350-6058]
dc.gnosis.orcid0000-0002-4350-6058


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