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dc.contributor.authorDikaiakos, Marios D.en
dc.contributor.authorSteiglitz, Kennethen
dc.contributor.authorRogers, Anneen
dc.contributor.editorAnonen
dc.creatorDikaiakos, Marios D.en
dc.creatorSteiglitz, Kennethen
dc.creatorRogers, Anneen
dc.date.accessioned2019-11-13T10:39:53Z
dc.date.available2019-11-13T10:39:53Z
dc.date.issued1994
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/53848
dc.description.abstractThis paper presents a comparison study of popular clustering and mapping heuristics which are used to map task-flow graphs to message-passing multiprocessors. To this end, we use task-graphs which are representative of important scientific algorithms running on data-sets of practical interest. The annotation which assigns weights to nodes and edges of the task-graphs is realistic. It reflects current trends in processor, communication channel, and message-passing interface technology and takes into consideration hardware characteristics of state-of-the-art multiprocessors. Our experiments show that applying realistic models for task-graph annotation affects the effectiveness and functionality of clustering and mapping techniques. Therefore, new heuristics are necessary that will take into account more practical models of communication costs. We present modifications to existing clustering and mapping algorithms which improve their efficiency and running-time for the practical models adopted.en
dc.publisherIEEEen
dc.sourceIEEE Symposium on Parallel and Distributed Processing - Proceedingsen
dc.sourceProceeedings of the 6th IEEE Symposium on Parallel and Distributed Processingen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-0028695008&partnerID=40&md5=b8a80607e9e61feed20e2a8fcf08335e
dc.subjectMathematical modelsen
dc.subjectComputer simulationen
dc.subjectParallel algorithmsen
dc.subjectMultiprocessing systemsen
dc.subjectGraph theoryen
dc.subjectCommunication channels (information theory)en
dc.subjectInterconnection networksen
dc.subjectParallel processing systemsen
dc.subjectComputer hardwareen
dc.subjectHeuristic methodsen
dc.subjectElectric network topologyen
dc.subjectInterfaces (computer)en
dc.subjectCommunication costen
dc.subjectMessage passing multiprocessorsen
dc.subjectData dependence graphen
dc.subjectInterconnection topologyen
dc.subjectInternalization phaseen
dc.subjectMapping heuristicsen
dc.subjectMapping parallel algorithmsen
dc.subjectParallel architectureen
dc.subjectParallel computeren
dc.subjectProcessor assignment phaseen
dc.titleComparison of techniques used for mapping parallel algorithms to message-passing multiprocessorsen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.description.startingpage434
dc.description.endingpage442
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: IEEEen
dc.description.notesConference code: 42406en
dc.description.notesCited By :5</p>en
dc.contributor.orcidDikaiakos, Marios D. [0000-0002-4350-6058]
dc.gnosis.orcid0000-0002-4350-6058


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