dc.contributor.author | Dikaiakos, Marios D. | en |
dc.contributor.author | Steiglitz, Kenneth | en |
dc.contributor.author | Rogers, Anne | en |
dc.contributor.editor | Anon | en |
dc.creator | Dikaiakos, Marios D. | en |
dc.creator | Steiglitz, Kenneth | en |
dc.creator | Rogers, Anne | en |
dc.date.accessioned | 2019-11-13T10:39:53Z | |
dc.date.available | 2019-11-13T10:39:53Z | |
dc.date.issued | 1994 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/53848 | |
dc.description.abstract | This paper presents a comparison study of popular clustering and mapping heuristics which are used to map task-flow graphs to message-passing multiprocessors. To this end, we use task-graphs which are representative of important scientific algorithms running on data-sets of practical interest. The annotation which assigns weights to nodes and edges of the task-graphs is realistic. It reflects current trends in processor, communication channel, and message-passing interface technology and takes into consideration hardware characteristics of state-of-the-art multiprocessors. Our experiments show that applying realistic models for task-graph annotation affects the effectiveness and functionality of clustering and mapping techniques. Therefore, new heuristics are necessary that will take into account more practical models of communication costs. We present modifications to existing clustering and mapping algorithms which improve their efficiency and running-time for the practical models adopted. | en |
dc.publisher | IEEE | en |
dc.source | IEEE Symposium on Parallel and Distributed Processing - Proceedings | en |
dc.source | Proceeedings of the 6th IEEE Symposium on Parallel and Distributed Processing | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028695008&partnerID=40&md5=b8a80607e9e61feed20e2a8fcf08335e | |
dc.subject | Mathematical models | en |
dc.subject | Computer simulation | en |
dc.subject | Parallel algorithms | en |
dc.subject | Multiprocessing systems | en |
dc.subject | Graph theory | en |
dc.subject | Communication channels (information theory) | en |
dc.subject | Interconnection networks | en |
dc.subject | Parallel processing systems | en |
dc.subject | Computer hardware | en |
dc.subject | Heuristic methods | en |
dc.subject | Electric network topology | en |
dc.subject | Interfaces (computer) | en |
dc.subject | Communication cost | en |
dc.subject | Message passing multiprocessors | en |
dc.subject | Data dependence graph | en |
dc.subject | Interconnection topology | en |
dc.subject | Internalization phase | en |
dc.subject | Mapping heuristics | en |
dc.subject | Mapping parallel algorithms | en |
dc.subject | Parallel architecture | en |
dc.subject | Parallel computer | en |
dc.subject | Processor assignment phase | en |
dc.title | Comparison of techniques used for mapping parallel algorithms to message-passing multiprocessors | en |
dc.type | info:eu-repo/semantics/conferenceObject | |
dc.description.startingpage | 434 | |
dc.description.endingpage | 442 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Conference Object | en |
dc.description.notes | <p>Sponsors: IEEE | en |
dc.description.notes | Conference code: 42406 | en |
dc.description.notes | Cited By :5</p> | en |
dc.contributor.orcid | Dikaiakos, Marios D. [0000-0002-4350-6058] | |
dc.gnosis.orcid | 0000-0002-4350-6058 | |