dc.contributor.author | Georgiou, Chryssis | en |
dc.contributor.author | Russell, A. | en |
dc.contributor.author | Shvartsman, A. A. | en |
dc.creator | Georgiou, Chryssis | en |
dc.creator | Russell, A. | en |
dc.creator | Shvartsman, A. A. | en |
dc.date.accessioned | 2019-11-13T10:40:12Z | |
dc.date.available | 2019-11-13T10:40:12Z | |
dc.date.issued | 2007 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/54004 | |
dc.description.abstract | The abstract problem of using P failure-prone processors to cooperatively update all locations of an N-element shared array is called Write-All. Solutions to Write-All can be used iteratively to construct efficient simulations of PRAM algorithms on failure-prone PRAMS. Such use of Write-All in simulations is abstracted in terms of the iterative Write-All problem. The efficiency of the algorithmic solutions for Write-All and iterative Write-All is measured in terms of work complexity where all processing steps taken by the processors are counted. This paper considers determinitic solutions for the Write-All and iterative Write-All problems in the fail-stop synchronous CRCW PRAM model where memory access concurrency needs to be controlled. A deterministic algorithm of Kanellakis, Michailidis, and Shvartsman [16] efficiently solves the Write-All problem in this model, while controlling read and write memory access concurrency. However it was not shown how the number of processor failures f affects the work efficiency of the algorithm. The results herein give a new analysis of the algorithm [16] that obtain failure-sensitive work bounds, while retaining the known memory access concurrency bounds. Specifically, the new result expresses the work bound as a function of N, P and f. Another contribution in this paper is the new failure-sensitive analysis for iterative Write-All with controlled memory access concurrency. This result yields tighter bounds on work (vs. [16]) for simulations of PRAM algorithms on fail-stop PRAMS. © World Scientific Publishing Company. | en |
dc.source | Parallel Processing Letters | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-34547334484&doi=10.1142%2fS0129626407002946&partnerID=40&md5=e13d122c5e6d397f11c1bd13f751d653 | |
dc.subject | Computer simulation | en |
dc.subject | Parallel algorithms | en |
dc.subject | Fault tolerance | en |
dc.subject | Concurrent engineering | en |
dc.subject | Programmable logic controllers | en |
dc.subject | Random access storage | en |
dc.subject | Storage allocation (computer) | en |
dc.subject | Fault-tolerance | en |
dc.subject | Work complexity | en |
dc.subject | Algorithm simulations | en |
dc.subject | Memory access concurrency | en |
dc.title | Failure-sensitive analysis of parallel algorithms with controlled memory access concurrency | en |
dc.type | info:eu-repo/semantics/article | |
dc.identifier.doi | 10.1142/S0129626407002946 | |
dc.description.volume | 17 | |
dc.description.issue | 2 | |
dc.description.startingpage | 153 | |
dc.description.endingpage | 168 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Article | en |
dc.description.notes | <p>Cited By :1</p> | en |
dc.source.abbreviation | Parallel Process Lett | en |
dc.contributor.orcid | Georgiou, Chryssis [0000-0003-4360-0260] | |
dc.gnosis.orcid | 0000-0003-4360-0260 | |