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dc.contributor.authorHardy, D.en
dc.contributor.authorSideris, I.en
dc.contributor.authorLadas, N.en
dc.contributor.authorSazeides, Yiannakisen
dc.creatorHardy, D.en
dc.creatorSideris, I.en
dc.creatorLadas, N.en
dc.creatorSazeides, Yiannakisen
dc.description.abstractThis paper presents a first-order analytical model for determining the performance degradation caused by permanently faulty cells in architectural and non-architectural arrays. We refer to this degradation as the performance vulnerability factor (PVF). The study assumes a future where cache blocks with faulty cells are disabled resulting in less cache capacity and extra misses while faulty predictor cells are still used but cause additional mispredictions. For a given program run, random probability of permanent cell failure, and processor configuration, the model can rapidly provide the expected PVF as well as lower and upper PVF probability distribution bounds for an individual array or array combination. The model is used to predict the PVF for the three predictors and the last level cache, used in this study, for a wide range of cell failure rates. The analysis reveals that for cell failure rate of up to 1.5e-6 the expected PVF is very small. For higher failure rates the expected PVF grows noticeably mostly due to the extra misses in the last level cache. The expected PVF of the predictors remains small even at high failure rates but the PVF distribution reveals cases of significant performance degradation with a non-negligible probability. These results suggest that designers of future processors can leverage trade-offs between PVF and reliability to sustain area, performance and energy scaling. The paper demonstrates this approach by exploring the implications of different cell size on yield and PVF. © 2012 IEEE.en
dc.sourceProceedings - 2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012en
dc.source2012 IEEE/ACM 45th International Symposium on Microarchitecture, MICRO 2012en
dc.subjectComputer architectureen
dc.subjectFailure analysisen
dc.subjectProbability distributionsen
dc.subjectProgram processorsen
dc.subjectCache blocksen
dc.subjectPermanent faultsen
dc.subjectCache capacityen
dc.subjectEnergy scalingen
dc.subjectFailure rateen
dc.subjectLast-level cachesen
dc.subjectPerformance degradationen
dc.subjectVulnerability factorsen
dc.titleThe performance vulnerability of architectural and non-architectural arrays to permanent faultsen
dc.description.endingpage59 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: AMDen
dc.description.notesIBM Researchen
dc.description.notesConference code: 96677en
dc.description.notesCited By :10</p>en

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