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dc.contributor.authorPetrides, P.en
dc.contributor.authorTrancoso, Pedroen
dc.creatorPetrides, P.en
dc.creatorTrancoso, Pedroen
dc.date.accessioned2019-11-13T10:41:58Z
dc.date.available2019-11-13T10:41:58Z
dc.date.issued2017
dc.identifier.isbn978-1-4503-5035-8
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/54828
dc.description.abstractAs the number of cores increases in a single chip processor, several challenges arise: wire delays, contention for out-ofchip accesses, and core heterogeneity. In order to address these issues and the applications demands, future large-scale many-core processors are expected to be organized as a collection of NUMA clusters of heterogeneous cores. In this work we propose a scheduler that takes into account the non-uniform memory latency, the heterogeneity of the cores, and the contention to the memory controller to find the best matching core for the application's memory and compute requirements. Scheduler decisions are based on an on-line classification process that determines applications requirements either as memory- or compute-bound. We evaluate our proposed scheduler on the 48-core Intel SCC using applications from SPEC CPU2006 benchmark suite. Our results show that even when all cores are busy, migrating processes to cores that match better the requirements of applications results in overall performance improvement. In particular we observed a reduction of the execution time from 15% to 36% compared to a random static scheduling policy. © 2017 ACM.en
dc.publisherAssociation for Computing Machinery, Incen
dc.sourceSYSTOR 2017 - Proceedings of the 10th ACM International Systems and Storage Conferenceen
dc.source10th ACM International Systems and Storage Conference, SYSTOR 2017en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85020694022&doi=10.1145%2f3078468.3078482&partnerID=40&md5=8dfa2d6e13435b2ae5db5e6aab0bbbb6
dc.subjectComputer architectureen
dc.subjectSchedulingen
dc.subjectBenchmarkingen
dc.subjectMany-core architectureen
dc.subjectMany-core processorsen
dc.subjectBenchmark suitesen
dc.subjectHeterogeneous coresen
dc.subjectMemory controlleren
dc.subjectOn-line classificationen
dc.subjectSingle chip processorsen
dc.subjectStatic schedulingen
dc.titleHeterogeneous- and NUMA-aware scheduling for many-core architecturesen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1145/3078468.3078482
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: ACM SIGOPSen
dc.description.noteset al.en
dc.description.notesIBMen
dc.description.notesNetAppen
dc.description.notesNokia Bell Labsen
dc.description.notesTechnion - Israel Institute of Technologyen
dc.description.notesConference code: 127850</p>en
dc.contributor.orcidTrancoso, Pedro [0000-0002-2776-9253]
dc.gnosis.orcid0000-0002-2776-9253


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