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dc.contributor.authorPrat-Pérez, A.en
dc.contributor.authorDominguez-Sal, D.en
dc.contributor.authorLarriba-Pey, J. -Len
dc.contributor.authorTrancoso, Pedroen
dc.creatorPrat-Pérez, A.en
dc.creatorDominguez-Sal, D.en
dc.creatorLarriba-Pey, J. -Len
dc.creatorTrancoso, Pedroen
dc.date.accessioned2019-11-13T10:42:05Z
dc.date.available2019-11-13T10:42:05Z
dc.date.issued2013
dc.identifier.issn0302-9743
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/54887
dc.description.abstractThe massive addition of cores on a chip is adding more pressure to the accesses to main memory. In order to avoid this bottleneck, we propose the use of a simple producer-consumer model, which allows for the temporary results to be transferred directly from one task to another. These data transfer operations are performed within the chip, using on-chip memory, thus avoiding costly off-chip memory accesses. We implement this model on a real many-core processor, the 48-core Intel Single-chip Cloud Computer processor using its on-chip memory facilities. We find that the Producer-Consumer model adapts to such architectures and allow to achieve good task and data parallelism. For the evaluation of the proposed platform we implement a graph-based application using the Producer- Consumer model. Our tests show that the model scales very well as it takes advantage of the on-chip memory. The execution times of our implementation are up to 9 times faster than the baseline implementation, which relies on storing the temporary results to main memory. © 2013 Springer-Verlag.en
dc.source26th International Conference on Architecture of Computing Systems, ARCS 2013en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84874200434&doi=10.1007%2f978-3-642-36424-2_10&partnerID=40&md5=4f9034232063c1723d5182c719e4fd1f
dc.subjectArtificial intelligenceen
dc.subjectData transferen
dc.subjectExecution timeen
dc.subjectMany-core processorsen
dc.subjectProgramming modelsen
dc.subjectData parallelismen
dc.subjectSingle-chip cloud computersen
dc.subjectGraph-baseden
dc.subjectMain memoryen
dc.subjectModel scaleen
dc.subjectOff-chip memoriesen
dc.subjectOn chip memoryen
dc.titleProducer-consumer: The programming model for future many-core processorsen
dc.typeinfo:eu-repo/semantics/article
dc.identifier.doi10.1007/978-3-642-36424-2_10
dc.description.volume7767 LNCSen
dc.description.startingpage110
dc.description.endingpage121
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeArticleen
dc.description.notes<p>Conference code: 95603</p>en
dc.source.abbreviationLect. Notes Comput. Sci.en
dc.contributor.orcidTrancoso, Pedro [0000-0002-2776-9253]
dc.gnosis.orcid0000-0002-2776-9253


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