dc.contributor.author | Prat-Pérez, A. | en |
dc.contributor.author | Dominguez-Sal, D. | en |
dc.contributor.author | Larriba-Pey, J. -L | en |
dc.contributor.author | Trancoso, Pedro | en |
dc.creator | Prat-Pérez, A. | en |
dc.creator | Dominguez-Sal, D. | en |
dc.creator | Larriba-Pey, J. -L | en |
dc.creator | Trancoso, Pedro | en |
dc.date.accessioned | 2019-11-13T10:42:05Z | |
dc.date.available | 2019-11-13T10:42:05Z | |
dc.date.issued | 2013 | |
dc.identifier.issn | 0302-9743 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/54887 | |
dc.description.abstract | The massive addition of cores on a chip is adding more pressure to the accesses to main memory. In order to avoid this bottleneck, we propose the use of a simple producer-consumer model, which allows for the temporary results to be transferred directly from one task to another. These data transfer operations are performed within the chip, using on-chip memory, thus avoiding costly off-chip memory accesses. We implement this model on a real many-core processor, the 48-core Intel Single-chip Cloud Computer processor using its on-chip memory facilities. We find that the Producer-Consumer model adapts to such architectures and allow to achieve good task and data parallelism. For the evaluation of the proposed platform we implement a graph-based application using the Producer- Consumer model. Our tests show that the model scales very well as it takes advantage of the on-chip memory. The execution times of our implementation are up to 9 times faster than the baseline implementation, which relies on storing the temporary results to main memory. © 2013 Springer-Verlag. | en |
dc.source | 26th International Conference on Architecture of Computing Systems, ARCS 2013 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84874200434&doi=10.1007%2f978-3-642-36424-2_10&partnerID=40&md5=4f9034232063c1723d5182c719e4fd1f | |
dc.subject | Artificial intelligence | en |
dc.subject | Data transfer | en |
dc.subject | Execution time | en |
dc.subject | Many-core processors | en |
dc.subject | Programming models | en |
dc.subject | Data parallelism | en |
dc.subject | Single-chip cloud computers | en |
dc.subject | Graph-based | en |
dc.subject | Main memory | en |
dc.subject | Model scale | en |
dc.subject | Off-chip memories | en |
dc.subject | On chip memory | en |
dc.title | Producer-consumer: The programming model for future many-core processors | en |
dc.type | info:eu-repo/semantics/article | |
dc.identifier.doi | 10.1007/978-3-642-36424-2_10 | |
dc.description.volume | 7767 LNCS | en |
dc.description.startingpage | 110 | |
dc.description.endingpage | 121 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Article | en |
dc.description.notes | <p>Conference code: 95603</p> | en |
dc.source.abbreviation | Lect. Notes Comput. Sci. | en |
dc.contributor.orcid | Trancoso, Pedro [0000-0002-2776-9253] | |
dc.gnosis.orcid | 0000-0002-2776-9253 | |