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dc.contributor.authorSazeides, Yiannakisen
dc.contributor.authorÖzer, E.en
dc.contributor.authorKershaw, D.en
dc.contributor.authorNikolaou, Panagiotaen
dc.contributor.authorKleanthous, Marios M.en
dc.contributor.authorAbella, J.en
dc.creatorSazeides, Yiannakisen
dc.creatorÖzer, E.en
dc.creatorKershaw, D.en
dc.creatorNikolaou, Panagiotaen
dc.creatorKleanthous, Mariosen
dc.creatorAbella, J.en
dc.date.accessioned2019-11-13T10:42:11Z
dc.date.available2019-11-13T10:42:11Z
dc.date.issued2013
dc.identifier.isbn978-1-4503-2638-4
dc.identifier.urihttp://gnosis.library.ucy.ac.cy/handle/7/54935
dc.description.abstractThis paper proposes implicit-storing to extend the logical capacity of a memory array without increasing its physical capacity by leveraging the array's error-correction-codes to infer the implicitly stored bits. Implicit-storing is related to error-code-tagging, a technique that distinguishes between faults in data and invariant attributes of a location when the attributes are not stored in the memory array but are encoded in the error-correction-codes. Both error-code-tagging and implicit-storing cause a code-strength reduction due to their encoding of additional information in the code meant to only protect data. Redundant-encoding-of-attributes is introduced to improve the strength of a code by encoding same information in multiple codewords in a cache or memory. We demonstrate how EREA and IREA, two derivatives of redundant-encoding, alleviate the code-strength reduction experienced by error-code-tagging and implicit-storing respectively. Implementing the proposed methods requires minor modifications in the encoding and decoding logic of the baseline error-correction scheme used in this work. The paper discusses several uses of the proposed schemes to help demonstrate their usefulness. © 2013 ACM.en
dc.sourceMICRO 2013 - Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitectureen
dc.source46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2013en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-84892513978&doi=10.1145%2f2540708.2540723&partnerID=40&md5=249b1ebb3deafed19cd0e3fc78e5efbf
dc.subjectComputer architectureen
dc.subjectreliabilityen
dc.subjectCache memoryen
dc.subjectEncoding (symbols)en
dc.subjectEncoding and decodingen
dc.subjectData storage equipmenten
dc.subjectProgram processorsen
dc.subjectmemoryen
dc.subjectMemory arrayen
dc.subjectCode-wordsen
dc.subjecterror code taggingen
dc.subjectError codesen
dc.subjecterror correction codesen
dc.subjectError-correction schemesen
dc.subjectimplicit storingen
dc.subjectredundant encodingen
dc.titleImplicit-storing and redundant-encoding-of-attribute information in error-correction-codesen
dc.typeinfo:eu-repo/semantics/conferenceObject
dc.identifier.doi10.1145/2540708.2540723
dc.description.startingpage160
dc.description.endingpage171
dc.author.faculty002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences
dc.author.departmentΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: ACM SIGMICROen
dc.description.notesIEEE TC-uARCHen
dc.description.notesConference code: 102006en
dc.description.notesCited By :2</p>en


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