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dc.contributor.authorTatas, Konstantinosen
dc.contributor.authorKyriacou, Costasen
dc.contributor.authorEvripidou, Paraskevasen
dc.contributor.authorTrancoso, Pedroen
dc.contributor.authorWong, S.en
dc.creatorTatas, Konstantinosen
dc.creatorKyriacou, Costasen
dc.creatorEvripidou, Paraskevasen
dc.creatorTrancoso, Pedroen
dc.creatorWong, S.en
dc.description.abstractThis paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45 slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated. © 2008 World Scientific Publishing Company.en
dc.sourceParallel Processing Lettersen
dc.subjectRapid prototypingen
dc.subjectInterconnection networksen
dc.subjectField programmable gate arrays (FPGA)en
dc.subjectMicroprocessor chipsen
dc.subjectData-driven multithreadingen
dc.subjectData flow analysisen
dc.subjectScheduling algorithmsen
dc.subjectThread Synchronization Unit (TSU)en
dc.subjectData-Driven Chip-Multiprocessorsen
dc.subjectFPGA implementationen
dc.titleRapid prototyping of the data-driven chip-multiprocessor (D 2-CMP) using FPGAsen
dc.description.endingpage306 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Πληροφορικής / Department of Computer Science
dc.source.abbreviationParallel Process Letten
dc.contributor.orcidTrancoso, Pedro [0000-0002-2776-9253]
dc.contributor.orcidEvripidou, Paraskevas [0000-0002-2335-9505]

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