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dc.contributor.authorZhao, W. S.en
dc.contributor.authorZhang, Y.en
dc.contributor.authorTrinh, H. -Pen
dc.contributor.authorKlein, J. -Oen
dc.contributor.authorChappert, C.en
dc.contributor.authorMantovan, R.en
dc.contributor.authorLamperti, A.en
dc.contributor.authorCowburn, R. P.en
dc.contributor.authorTrypiniotis, Theodossisen
dc.contributor.authorKlaui, M.en
dc.contributor.authorHeinen, J.en
dc.contributor.authorOcker, B.en
dc.contributor.authorRavelosona, D.en
dc.creatorZhao, W. S.en
dc.creatorZhang, Y.en
dc.creatorTrinh, H. -Pen
dc.creatorKlein, J. -Oen
dc.creatorChappert, C.en
dc.creatorMantovan, R.en
dc.creatorLamperti, A.en
dc.creatorCowburn, R. P.en
dc.creatorTrypiniotis, Theodossisen
dc.creatorKlaui, M.en
dc.creatorHeinen, J.en
dc.creatorOcker, B.en
dc.creatorRavelosona, D.en
dc.description.abstractThe racetrack memory device is a new concept of Magnetic RAM (MRAM) based on controlling domain wall (DW) motion in ferromagnetic nanowires. It promises ultra-high storage density thanks to the possibility to store multiple narrow DWS per memory cell. By using read and write heads based on magnetic tunnel junctions (MTJ) with perpendicular magnetic anisotropy (PMA) fast data access speed can also be achieved. Thereby the racetrack memory can be used as universal storage to address both embedded and standalone applications. In this paper, we present the device physics, integration circuit and architecture designs of a racetrack memory based on MTJs with PMA. Mixed SPICE simulations at 65 nm node demonstrate the capabilities of this device to perform high performances. Finally, we compare the potential specifications of the racetrack memory with other advanced non-volatile memory technologies. © 2012 IEEE.en
dc.sourceICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedingsen
dc.source2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012en
dc.subjectRandom access storageen
dc.subjectMagnetic tunnel junctionen
dc.subjectData storage equipmenten
dc.subjectArchitecture designsen
dc.subjectDomain wall motionen
dc.subjectFerromagnetic nanowireen
dc.subjectIntegration circuitsen
dc.subjectMagnetic devicesen
dc.subjectMagnetic domainsen
dc.subjectMRAM devicesen
dc.subjectNon-volatile memory technologyen
dc.subjectPerpendicular magnetic anisotropyen
dc.subjectStandalone applicationsen
dc.titleMagnetic domain-wall racetrack memory for high density and fast data storageen
dc.identifier.doi10.1109/ICSICT.2012.6466687Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Φυσικής / Department of Physics
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: IEEE Beijing Sectionen
dc.description.notesFudan Universityen
dc.description.notesXidian Universityen
dc.description.notesIEEE Electron Devices Society Shanghai Chapteren
dc.description.notesIEEE SSCS Shanghai Chapteren
dc.description.notesConference code: 95953en
dc.description.notesCited By :13</p>en

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