Browsing by Author "Sazeides, Yiannakis"

Now showing items 21-40 of 59

    • Conference Object  

      GeST: An Automatic Framework For Generating CPU Stress-Tests 

      Hadjilambrou, Zacharias; Das, Shidhartha; Whatmough, Paul N; Bull, David; Sazeides, Yiannakis (2019)
      This work presents GeST (Generator for Stress-Tests): a framework for automatically generating CPU stress-tests. The framework is based on genetic algorithm search and can be used to maximize different target CPU metrics ...
    • Book Chapter  

      The HARPA Approach to Ensure Dependable Performance 

      Zompakis, Nikolaos; Noltsis, Michail; Nikolaou, Panagiota; Englezakis, Panayiotis; Hadjilambrou, Zacharias; Ndreu, Lorena; Massari, Giuseppe; Libutti, Simone; Portero, Antoni; Sassi, Federico; Bacchini, Alessandro; Nicopoulos, Chrysostomos; Sazeides, Yiannakis; Vavrik, Radim; Golasowski, Martin; Sevcik, Jiri; Kuchar, Stepan; Vondrak, Vit; Agnes, Fritsch; Cappelle, Hans; Catthoor, Francky; Fornaciari, William; Soudris, Dimitrios (Springer International Publishing, 2019)
      The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively ...
    • Book Chapter  

      The HARPA Approach to Ensure Dependable Performance 

      Zompakis, Nikolaos; Noltsis, Michail; Nikolaou, Panagiota; Englezakis, Panayiotis; Hadjilambrou, Zacharias; Ndreu, Lorena; Massari, Giuseppe; Libutti, Simone; Portero, Antoni; Sassi, Federico; Bacchini, Alessandro; Nicopoulos, Chrysostomos; Sazeides, Yiannakis; Vavrik, Radim; Golasowski, Martin; Sevcik, Jiri; Kuchar, Stepan; Vondrak, Vit; Agnes, Fritsch; Cappelle, Hans; Catthoor, Francky; Fornaciari, William; Soudris, Dimitrios (Springer International Publishing, 2019)
      The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively ...
    • Conference Object  

      HARPA: Solutions for dependable performance under physically induced performance variability 

      Rodopoulos, Dimitrios; Corbetta, S.; Massari, Giuseppe; Libutti, S.; Catthoor, F.; Sazeides, Yiannakis; Nicopoulos, Chrysostomos A.; Portero, Antoni; Cappe, E.; Vavrík, R.; Vondrák, V.; Soudris, Dimitrios J.; Sassi, F.; Fritsch, A.; Fornaciari, W. (Institute of Electrical and Electronics Engineers Inc., 2015)
      Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need ...
    • Conference Object  

      HARPA: Tackling physically induced performance variability 

      Zompakis, Nikolaos; Noltsis, Michail; Ndreu, L.; Hadjilambrou, Zacharias; Englezakis, Panayiotis; Nikolaou, Panagiota; Portero, Antoni; Libutti, S.; Massari, Giuseppe; Sassi, F.; Bacchini, A.; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis; Vavrik, R.; Golasowski, M.; Sevcik, J.; Vondrak, V.; Catthoor, F.; Fornaciari, W.; Soudris, Dimitrios J. (Institute of Electrical and Electronics Engineers Inc., 2017)
      Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an everlasting scaling of devices in silicon. Nevertheless, ...
    • Conference Object  

      How to compare the performance of two SMT microarchitectures 

      Sazeides, Yiannakis; Juan, T. (Institute of Electrical and Electronics Engineers Inc., 2001)
      In this paper we discuss methods and metrics for comparing the performance of two simultaneous multithreading microarchitectures. We identify conditions under which the instructions-per-cycle metric may be misleading for ...
    • Conference Object  

      Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes 

      Sazeides, Yiannakis; Özer, E.; Kershaw, D.; Nikolaou, Panagiota; Kleanthous, Marios M.; Abella, J. (2013)
      This paper proposes implicit-storing to extend the logical capacity of a memory array without increasing its physical capacity by leveraging the array's error-correction-codes to infer the implicitly stored bits. ...
    • Article  

      Improving branch prediction by considering affectors and affectees correlations 

      Sazeides, Yiannakis; Moustakas, Andreas; Constantinides, Kypros; Kleanthous, Marios M. (2011)
      This work investigates the potential of direction-correlations to improve branch prediction. There are two types of direction-correlation: affectors and affectees. This work considers for the first time their implications ...
    • Article  

      Instruction-Isomorphism in program execution 

      Sazeides, Yiannakis (2003)
      This paper identifies a fundamental runtime program property: Instruction-Isomorphism. An instruction instance is said to be isomorphic if its component - Information derived from the instruction and its backward dynamic ...
    • Conference Object  

      Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization 

      Hadjilambrou, Zacharias; Das, Shidhartha; Antoniades, Marco A.; Sazeides, Yiannakis (2018)
      Worst-case dI/dt voltage noise is typically characterized post-silicon using direct voltage measurements through either on-package measurement points or on-chip dedicated circuitry. These approaches consume expensive pad ...
    • Article  

      Limits of data value predictability 

      Sazeides, Yiannakis; Smith, J. E. (1999)
      The predictability of data values is studied at a fundamental level. Two basic predictor models are defined: Computational predictors perform an operation on previous values to yield predicted next values. Examples we study ...
    • Conference Object  

      Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs 

      Tovletoglou, Konstantinos; Mukhanov, Lev; Karakonstantis, Georgios; Chatzidimitriou, Athanasios; Papadimitriou, George; Kaliorakis, Manolis; Gizopoulos, Dimitris; Hadjilambrou, Zacharias; Sazeides, Yiannakis; Lampropulos, Alejandro; Das, Shidhartha; Vo, Phong (2018)
      In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, we ...
    • Conference Object  

      Memory array protection: Check on read or check on write? 

      Nikolaou, Panagiota; Sazeides, Yiannakis; Ndreu, L.; Özer, E.; Idgunji, S. (2013)
      This work introduces Check-on-Write: a memory array error protection approach that enables a trade-off between a memory array's fault-coverage and energy. The presented approach checks for error in a value stored in an ...
    • Conference Object  

      Modeling program predictability 

      Sazeides, Yiannakis; Smith, James E. (IEEE Comp Soc, 1998)
      Basic properties of program predictability - for both values and control - are defined and studied. We take the view that program predictability originates at certain points during a program's execution, flows through ...
    • Article  

      Modeling the impact of permanent faults in caches 

      Sánchez, D.; Sazeides, Yiannakis; Cebrián, J. M.; Garćia, J. M.; Aragón, J. L. (2013)
      The traditional performance cost benefits we have enjoyed for decades from technology scaling are challenged by several critical constraints including reliability. Increases in static and dynamic variations are leading to ...
    • Conference Object  

      Modeling the implications of DRAM failures and protection techniques on datacenter TCO 

      Nikolaou, Panagiota; Sazeides, Yiannakis; Ndreu, L.; Kleanthous, Marios M. (IEEE Computer Society, 2015)
      Total Cost of Ownership (TCO) is a key optimization metric for the design of a datacenter. This paper proposes, for the first time, a framework for modeling the implications of DRAM failures and DRAM error protection ...
    • Conference Object  

      Modeling value speculation 

      Sazeides, Yiannakis (IEEE Computer Society, 2002)
      Several studies of speculative execution based on values have reported promising performance potential. However, virtually all microarchitectures in these studies were described in an ambiguous manner, mainly due to the ...
    • Book Chapter  

      Monitor and Knob Techniques in Network-on-Chip Architectures 

      Zoni, Davide; Englezakis, Panayiotis; Chrysanthou, Kypros; Canidio, Andrea; Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos; Sazeides, Yiannakis; Fornaciari, William (Springer International Publishing, 2019)
      This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and ...
    • Book Chapter  

      Monitor and Knob Techniques in Network-on-Chip Architectures 

      Zoni, Davide; Englezakis, Panayiotis; Chrysanthou, Kypros; Canidio, Andrea; Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos; Dimitrakopoulos, Giorgos; Sazeides, Yiannakis; Fornaciari, William (Springer International Publishing, 2019)
      This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and ...
    • Conference Object  

      NoCAlert: An on-line and real-time fault detection mechanism for network-on-chip architectures 

      Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis (2012)
      The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming increasingly susceptible to emerging reliability ...