Browsing Τμήμα Πληροφορικής / Department of Computer Science by Author "Nicopoulos, Chrysostomos A."

Now showing items 1-8 of 8

    • Article  

      BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 

      Zoni, D.; Canidio, A.; Fornaciari, W.; Englezakis, Panayiotis; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis (2017)
      The Network-on-Chip (NoC) router buffers play an instrumental role in the performance of both the interconnection fabric and the entire multi-/many-core system. Nevertheless, the buffers also constitute the major leakage ...
    • Conference Object  

      HARPA: Solutions for dependable performance under physically induced performance variability 

      Rodopoulos, Dimitrios; Corbetta, S.; Massari, Giuseppe; Libutti, S.; Catthoor, F.; Sazeides, Yiannakis; Nicopoulos, Chrysostomos A.; Portero, Antoni; Cappe, E.; Vavrík, R.; Vondrák, V.; Soudris, Dimitrios J.; Sassi, F.; Fritsch, A.; Fornaciari, W. (Institute of Electrical and Electronics Engineers Inc., 2015)
      Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need ...
    • Conference Object  

      HARPA: Tackling physically induced performance variability 

      Zompakis, Nikolaos; Noltsis, Michail; Ndreu, L.; Hadjilambrou, Zacharias; Englezakis, Panayiotis; Nikolaou, Panagiota; Portero, Antoni; Libutti, S.; Massari, Giuseppe; Sassi, F.; Bacchini, A.; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis; Vavrik, R.; Golasowski, M.; Sevcik, J.; Vondrak, V.; Catthoor, F.; Fornaciari, W.; Soudris, Dimitrios J. (Institute of Electrical and Electronics Engineers Inc., 2017)
      Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an everlasting scaling of devices in silicon. Nevertheless, ...
    • Conference Object  

      NoCAlert: An on-line and real-time fault detection mechanism for network-on-chip architectures 

      Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis (2012)
      The widespread proliferation of the Chip Multi-Processor (CMP) paradigm has cemented the criticality of the on-chip interconnection fabric. The Network-on-Chip (NoC) is becoming increasingly susceptible to emerging reliability ...
    • Article  

      An online and real-time fault detection and localization mechanism for network-on-chip architectures 

      Chrysanthou, Kypros; Englezakis, Panayiotis; Prodromou, Andreas; Panteli, Andreas; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis; Dimitrakopoulos, Giorgos N. (2016)
      Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability threats. The need to detect and localize the occurrence of faults at runtime is steadily becoming imperative. In this work, we propose ...
    • Article  

      Optimizing data-center tco with scale-out processors 

      Grot, B.; Hardy, D.; Lotfi-Kamran, P.; Falsafi, B.; Nicopoulos, Chrysostomos A.; Sazeides, Yiannakis (2012)
      Performance and total cost of ownership (TCO) are key optimization metrics in large-scale data centers. According to these metrics, data centers designed with conventional server processors are inefficient. Recently ...
    • Conference Object  

      Thermal characterization of cloud workloads on a power-efficient server-on-chip 

      Milojevic, D.; Idgunji, S.; Jevdjic, D.; Ozer, E.; Lotfi-Kamran, P.; Panteli, Andreas; Prodromou, Andreas; Nicopoulos, Chrysostomos A.; Hardy, D.; Falsari, B.; Sazeides, Yiannakis (2012)
      We propose a power-efficient many-core server-on-chip system with 3D-stacked Wide I/O DRAM targeting cloud workloads in datacenters. The integration of 3D-stacked Wide I/O DRAM on top of a logic die increases available ...
    • Article  

      Toward multi-layer holistic evaluation of system designs 

      Kleanthous, Marios M.; Sazeides, Yiannakis; Ozer, E.; Nicopoulos, Chrysostomos A.; Nikolaou, Panagiota; Hadjilambrou, Zacharias (2016)
      The common practice for quantifying the benefit(s) of design-time architectural choices of server processors is often limited to the chip- or server-level. This quantification process invariably entails the use of salient ...