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dc.contributor.authorDikaiakos, Marios D.en
dc.contributor.authorSteiglitz, Kennethen
dc.creatorDikaiakos, Marios D.en
dc.creatorSteiglitz, Kennethen
dc.description.abstractAchieving efficient and reliable synchronization is a critical problem in building long systolic arrays. This problem is addressed in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. Analytic bounds are presented for the probability of failure, and an examination is made of the tradeoffs between reliability and throughput in both schemes. The basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes preferable to straight-line clocking.en
dc.publisherPubl by IEEEen
dc.sourceProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processingen
dc.sourceProceedings of the 1991 International Conference on Acoustics, Speech, and Signal Processing - ICASSP 91en
dc.subjectFailure Analysisen
dc.subjectClock distribution schemesen
dc.subjectComputer Architectureen
dc.subjectMathematical Techniques--Treesen
dc.subjectStraight-line clockingen
dc.subjectSystolic arraysen
dc.subjectTree clockingen
dc.titleComparison of tree and straight-line clocking for long systolic arraysen
dc.description.endingpage1180 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Πληροφορικής / Department of Computer Science
dc.type.uhtypeConference Objecten
dc.description.notes<p>Sponsors: IEEE Signal Processing Socen
dc.description.notesConference code: 16306en
dc.description.notesCited By :2</p>en
dc.contributor.orcidDikaiakos, Marios D. [0000-0002-4350-6058]

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