dc.contributor.author | Otoom, M. | en |
dc.contributor.author | Jaleel, A. | en |
dc.contributor.author | Trancoso, Pedro | en |
dc.creator | Otoom, M. | en |
dc.creator | Jaleel, A. | en |
dc.creator | Trancoso, Pedro | en |
dc.date.accessioned | 2019-11-13T10:41:34Z | |
dc.date.available | 2019-11-13T10:41:34Z | |
dc.date.issued | 2017 | |
dc.identifier.isbn | 978-1-4503-4487-6 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/54661 | |
dc.description.abstract | The trend of increasing the number of cores in a processor will lead to certain challenges, among which the fact that more cores issue more memory requests and this in turn will increase the competition, or interference, for shared resources such as the Last-Level Cache (LLC). In this work we focus on the cache interference while executing Decision Support System queries, which is a common case for a Data Center scenario. We study the co-execution of different queries from the TPC-H benchmark using the PostgreSQL DBMS system on a multicore with up to 16 cores and different LLC configurations. In addition to the working set metric, to better understand the effects of co-execution, we develop two new "personality" metrics to classify the behavior of the queries in co-execution: social and sensitive metrics. These metrics can be used to manage the cache interference and thus improve the co-execution performance of the queries. © 2017 Copyright held by the owner/author(s). | en |
dc.publisher | Association for Computing Machinery, Inc | en |
dc.source | ACM International Conference on Computing Frontiers 2017, CF 2017 | en |
dc.source | 14th ACM International Conference on Computing Frontiers, CF 2017 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85020752135&doi=10.1145%2f3075564.3075591&partnerID=40&md5=4ade7e483faac6038340f41dbc45c7e5 | |
dc.subject | Cache | en |
dc.subject | Multi-cores | en |
dc.subject | Database workload | en |
dc.subject | Performance Metrics | en |
dc.title | Using personality metrics to improve cache interference management in multicore processors | en |
dc.type | info:eu-repo/semantics/conferenceObject | |
dc.identifier.doi | 10.1145/3075564.3075591 | |
dc.description.startingpage | 251 | |
dc.description.endingpage | 254 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Conference Object | en |
dc.description.notes | <p>Sponsors: ACM SIGMICRO | en |
dc.description.notes | E4 Computer Engineering | en |
dc.description.notes | et al. | en |
dc.description.notes | IBM | en |
dc.description.notes | INTEL | en |
dc.description.notes | University of Siena | en |
dc.description.notes | Conference code: 128277 | en |
dc.description.notes | Cited By :1</p> | en |
dc.contributor.orcid | Trancoso, Pedro [0000-0002-2776-9253] | |
dc.gnosis.orcid | 0000-0002-2776-9253 | |