Energy efficient stream-based configurable architecture for embedded platforms
SourceProceedings - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012
2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012
Google Scholar check
MetadataShow full item record
Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology that adopts the stream-based computing model and the usage of Graphics Processing Units as prototyping platforms. In this paper we go a step further and propose a new modular architecture for low-power reconfigurable systems to easily map the stream-based algorithms. In particular, the architecture consists of a semi-programable accelerator set that can be adapted to the application needs in terms of functional units and number of streaming engines. The proposed embedded architecture mates the flexibility of reconfigurable hardware with the advantages of stream computing for the strict needs of embedded reconfigurable devices. We show a possible organization for this architecture. Moreover, we provide a general case study to analyze the scalability of the proposed architecture in an Altera FPGA. Our experimental results show that a significant speed-up can be achieved compared to general purpose processors using low-power FPGA devices. Our preliminary estimates show that it is also possible to achieve energy savings of up to 118x. © 2012 IEEE.
Showing items related by title, author, creator and subject.
DART: a data-driven processor architecture for real-time computing Farquhar, William G.; Evripidou, Paraskevas (Publ by Elsevier Science Publishers B.V., 1993)This paper presents the design of DART, a Data-driven processor Architecture for Real-Time computing. The DART processor is designed to be the key building block in real-time multiprocessor systems that can handle multiple ...
A pluggable and reconfigurable architecture for a context-aware enabling middleware system Paspallis, Nearchos; Rouvoy, R.; Barone, P.; Papadopoulos, George Angelos; Eliassen, F.; Mamelli, Alessandro (2008)Context awareness is a core feature of modern mobile and ubiquitous computing systems. Although it has not reached its full potential yet, one can already observe significant activity in the area of software engineering ...
D3-machine: A decoupled data-driven multithreaded architecture with variable resolution support Evripidou, Paraskevas (2001)This paper presents the Decoupled Data-Driven machine (D3-machine), a multithreaded architecture with data-driven synchronization. The D3-machine is an efficient and cost-effective design that combines the advantages of ...