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dc.contributor.authorSeznec, A.en
dc.contributor.authorFelix, S.en
dc.contributor.authorKrishnan, V.en
dc.contributor.authorSazeides, Yiannakisen
dc.creatorSeznec, A.en
dc.creatorFelix, S.en
dc.creatorKrishnan, V.en
dc.creatorSazeides, Yiannakisen
dc.description.abstractThis paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture featuring a very deep pipeline and simultaneous multithreading. Performance of such a processor is highly dependent on the accuracy of its branch predictor and consequently a very large silicon area was devoted to branch prediction on EV8. The Alpha EV8 branch predictor relies on global history and features a total of 352 Kbits. The focus of this paper is on the different trade-offs performed to overcome various implementation constraints for the EV8 branch predictor. One such instance is the pipelining of the predictor on two cycles to facilitate the prediction of up to 16 branches per cycle from any two dynamically successive, 8 instruction fetch blocks. This resulted in the use of three fetch-block old compressed branch history information for accesing the predictor. Implementation constraints also restricted the composition of the index functions for the predictor and forced the usage of only single-ported memory cells. Nevertheless, we show that the Alpha EV8 branch predictor achieves prediction accuracy in the same range as the state-of-the-art academic global history branch predictors that do not consider implementation constraints in great detail.en
dc.sourceConference Proceedings - Annual International Symposium on Computer Architecture, ISCAen
dc.subjectComputer simulationen
dc.subjectComputer hardwareen
dc.subjectMicroprocessor chipsen
dc.subjectBranch predictoren
dc.titleDesign tradeoffs for the Alpha EV8 conditional branch predictoren
dc.description.endingpage306 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied SciencesΤμήμα Πληροφορικής / Department of Computer Science
dc.description.notes<p>Cited By :90</p>en
dc.source.abbreviationConf Proc Annu Int Symp Comput Archit ISCAen

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