Approximating standard cell delay distributions by reformulating the most probable failure point
Date
2016Author
Rodopoulos, DimitriosRoussel, P.
Catthoor, F.
Sazeides, Yiannakis
Soudris, Dimitrios J.
Publisher
CEUR-WSSource
CEUR Workshop ProceedingsWorkshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, ERMAVSS 2016
Volume
1566Pages
13-16Google Scholar check
Keyword(s):
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Show full item recordAbstract
The delay distribution of a digital circuit path is crucial for the early reliability evaluation of a digital design. As transistors are shrunk to unprecedented dimensions, accurate yet fast estimation of such distributions remains a valid goal. Such distributions may not be provided or are delivered in a heavily abstracted fashion to designers, which reduces the insight into design dependability. In view of the above observations, we propose a technique that approximates the probability density function of a path of digital circuits by exending a well-known computational kernel, namely the Most Probable Failure Point (MPFP) technique. The output of this concept is the failure probability of standard cells or paths there of for various target delays. We reformulate MPFP and establish a concise methodology for delay distribution approximation. We present simulations for an inverter and outline projections for more complex gates. Copyright © 2016 for the individual papers by the papers' authors.