dc.contributor.author | Rodopoulos, Dimitrios | en |
dc.contributor.author | Roussel, P. | en |
dc.contributor.author | Catthoor, F. | en |
dc.contributor.author | Sazeides, Yiannakis | en |
dc.contributor.author | Soudris, Dimitrios J. | en |
dc.contributor.editor | Evans A. | en |
dc.contributor.editor | di Carlo S. | en |
dc.contributor.editor | Raghavan P. | en |
dc.contributor.editor | Gizopoulos D. | en |
dc.creator | Rodopoulos, Dimitrios | en |
dc.creator | Roussel, P. | en |
dc.creator | Catthoor, F. | en |
dc.creator | Sazeides, Yiannakis | en |
dc.creator | Soudris, Dimitrios J. | en |
dc.date.accessioned | 2019-11-13T10:42:07Z | |
dc.date.available | 2019-11-13T10:42:07Z | |
dc.date.issued | 2016 | |
dc.identifier.uri | http://gnosis.library.ucy.ac.cy/handle/7/54900 | |
dc.description.abstract | The delay distribution of a digital circuit path is crucial for the early reliability evaluation of a digital design. As transistors are shrunk to unprecedented dimensions, accurate yet fast estimation of such distributions remains a valid goal. Such distributions may not be provided or are delivered in a heavily abstracted fashion to designers, which reduces the insight into design dependability. In view of the above observations, we propose a technique that approximates the probability density function of a path of digital circuits by exending a well-known computational kernel, namely the Most Probable Failure Point (MPFP) technique. The output of this concept is the failure probability of standard cells or paths there of for various target delays. We reformulate MPFP and establish a concise methodology for delay distribution approximation. We present simulations for an inverter and outline projections for more complex gates. Copyright © 2016 for the individual papers by the papers' authors. | en |
dc.publisher | CEUR-WS | en |
dc.source | CEUR Workshop Proceedings | en |
dc.source | Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, ERMAVSS 2016 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84964561115&partnerID=40&md5=8f243df883c880adff865c82157ffc6b | |
dc.subject | Design | en |
dc.subject | Probability density function | en |
dc.subject | Reliability | en |
dc.subject | Reconfigurable hardware | en |
dc.subject | Complex gates | en |
dc.subject | Computational kernels | en |
dc.subject | Delay circuits | en |
dc.subject | Delay distributions | en |
dc.subject | Digital circuits | en |
dc.subject | Digital designs | en |
dc.subject | Failure Probability | en |
dc.subject | Fast estimation | en |
dc.subject | Most probable failure point | en |
dc.subject | Reliability Evaluation | en |
dc.title | Approximating standard cell delay distributions by reformulating the most probable failure point | en |
dc.type | info:eu-repo/semantics/conferenceObject | |
dc.description.volume | 1566 | |
dc.description.startingpage | 13 | |
dc.description.endingpage | 16 | |
dc.author.faculty | 002 Σχολή Θετικών και Εφαρμοσμένων Επιστημών / Faculty of Pure and Applied Sciences | |
dc.author.department | Τμήμα Πληροφορικής / Department of Computer Science | |
dc.type.uhtype | Conference Object | en |
dc.description.notes | <p>Sponsors: Cross-Layer Early Reliability Evaluation for the Computing Continuum (CLERECO) | en |
dc.description.notes | Modelling Reliability under Variability (MORV) | en |
dc.description.notes | Conference code: 119954</p> | en |